I got to a point where I could disassemble the ROM that I needed to, and then I lost momentum. Then life happened, and then next thing you know I don’t even remember how to run nono on my laptop. Luckly, I was able to rebuild some of the context and get back into the mindset of writing a Ghidra processor definition with SLEIGH. I took inventory and it looks like the end could be in reach. I also submitted a proposal to talk at VCF-E 2024 about writing Ghidra processor definitions, so this really better get done before April.
Also Kai Nacke pointed me to valid.s which has all the valid istructions in assembly format. I managed to assemble that barring one instruction, and now have a binary file that concretely shows me what can’t be dissasembled with the current definition. With that I can start crossing of the instructions as I make progress.
For the record the remaining bits are:
- add.ci, .co, .cio, addu.ci, .co, .cio, sub.ci .co .cio, subu.ci .co cio
- bcnd, tcnd does not do mnemonics
- fadd, fcmp, fdiv, ff0, ff1, flt, fmul, fsub, fxcr
- ld *.usr scalled and unscalled
- st *.usr scalled and unscalled
- xmem scaled and unscaled
And I feel like I can see the light at the end of the tunnel.